1. Technical Field
Methods of forming a copper wiring in a semiconductor device are disclosed which are capable of preventing an electrical short condition between neighboring copper wirings and facilitating subsequent processes. The disclosed methods accomplish this through surface polishing, and by prohibiting electro-migration and stress migration of copper in the copper wiring formed within a damascene pattern.
2. Discussion of Related Art
Generally, as the semiconductor industry shifts to an ultra large-scale integration (ULSI) level, the geometry of the devices continue to be narrowed to a sub-half-micron region. In view of improved performance and reliability, circuit density is gradually increased. Copper has a high resistance to electro-migration (EM) since it has a higher melting point than aluminum. Thus, copper can improve reliability of the devices. Further, copper can increase a signal transfer speed since it has a low resistivity. For this reason, in forming a metal wiring in a semiconductor device, copper has been used as an interconnection material useful for an integration circuit.
Methods of burying copper that may be used currently include physical vapor deposition (PVD) method/a reflow, chemical vapor deposition (CVD), electroplating, electroless-plating, and the like. Preferred methods are electroplating and CVD, both of which have a relatively good copper burial characteristic.
While copper is used as a material of a metal wiring, a damascene scheme for simultaneously forming a via contact hole for electrical connection to a lower layer and a trench in which the metal wiring is located, has been widely used along with a process of forming a copper wiring in a semiconductor device. A low-dielectric insulating material having a low dielectric constant is used as an interlayer insulating film in which a damascene pattern will be formed.
In order to form a copper wiring in the damascene pattern having the via contact hole and the trench, copper is buried into the damascene pattern through several methods and the buried copper layer is then polished by a chemical mechanical polishing (CMP) process, so that the buried copper layer is isolated from neighboring copper wirings.
FIG. 1 is a sectional view for explaining the conventional method of forming the copper wiring.
A first interlayer insulating film 12 and an anti-polishing layer 13 are formed on a substrate 11. The anti-polishing layer 13 and the first interlayer insulating film 12 are etched by a damascene scheme to form a damascene pattern 14.
A copper anti-diffusion conductive film 15 is formed along the surface of the anti-polishing layer 13 including the damascene pattern 14. A copper layer is formed to sufficiently bury the damascene pattern 14. A CMP process is then performed until the anti-polishing layer 13 is exposed, thus forming a copper wiring 16 within the damascene pattern 14. Thereafter, a copper anti-diffusion insulating film 100 and a second interlayer insulating film 17 are formed on the entire structure including the copper wiring 16.
In the above-mentioned method, in order to prevent diffusion of copper elements from the copper wiring 16, the copper wiring 16 is sealed using the copper anti-diffusion conductive film 15 and the copper anti-diffusion insulating film 100. In a device having the copper wiring 16 formed by a conventional method, however, most of defective wirings are generated due to electro-migration and stress migration that take place at the interface between the copper anti-diffusion insulating film 100 and the copper anti-diffusion conductive film 15, as indicated by an arrow “A”. This condition is caused by a lack in the bondability between the copper anti-diffusion insulating film 100 and the underlying layers 13, 15 and 16.